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Random Number Generator Board
The board is inserted vertically(M) (L)
Random Number Generator Schematic
Inspired by other designs I've seen online, most directly Rob Seward's design, I decided to build my own random number generator based Will Ware's "avalanche noise in a reverse-biased PN junction" (try this mirror of Will Ware's page)

I also read about the ORB Random Bit Generator which mostly reminded me to consider the low-order bits of the ADC reading.

My circuit uses a MAX680 to produce ∼±10V so that I have the requisite 18V across the PN junction. At $4 (qty 1) you may be better off choosing a MAX232-type chip and ignoring the receive/transmit functionality.

Originally I used the LSBs of the ADC, following the lead of Seward by using ADC, and the insight of the ORB project to use LSBs rather than MSBs. This led to low data rates (as low as 1KB/s), so instead I decided to use the amplified noise as a digital input. Digital inputs can be sampled at a much higher rate, so even if more samples are required to get a random output byte, the data rate can be higher. I attained a rate of over 50KiB/s while passing the dieharder suite of random number tests.

The package includes a program to read random numbers, and one to add random numbers to the linux /dev/random entropy pool. These programs are written in Python and require pyserial (Ubuntu package name: python-serial).

Because of the baud rate used (2Mbps), Linux users will require pyserial 2.3 or above.

For more details, see the README and source code included in the zip file.

The astute eye will notice that there's a resistor in the board photo which is not present in the design files. This reflects an earlier revision of the circuit, in which ANALOG0 had a resistive divider R3:R4 as in Seward's design (but value 4.7k in both cases). R4 pulled the voltage down so low that it never reached the minimum voltage to provide a "1" input. I clipped it on my board and removed it from the design files.

Files currently attached to this page:

rng.zip49.5kB



Entry first conceived on 10 November 2009, 16:00 UTC, last modified on 10 November 2009, 16:39 UTC



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